Seminars
Acceleration of Design Verification utilizing FPGAs and GPGPUs
Takeshi Matsumoto
Thu, Oct. 4th, 2012, 1:30 p.m., Room TR2100
Abstract
System designs including hardware such as embedded system and system-on-chip keep becoming larger and more complicated. This trend makes verification more and more difficult and time consuming. Recently, acceleration by hardware devices such as FPGA and GPGPU has drawn much attention. Those devices provide very high concurrency in computation compared to CPUs. In this presentation, we introduce two of our projects to accelerate verification by such devices. The first work is assertion extraction in gate-level simulation using GPGPU. The method examines whether a logical relation is satisfied among a set of signals in simulation results. The second is an implementation of statistical model checking by FPGA. We show an example system to verify wave propagation by statistical model checking, which statistically checks temporal properties on wave heights. In both methods, we show the performance improvement compared to execution by CPUs, through the experimental results.
SoC Monitoring and Debugging Technologies and their Application in a 3D Graphics SoC
Prof. Ing-Jer Huang
Wednesday, Aug. 10th, 1:00 p.m., Room MC603
Abstract
The ever increasing complexity of SoC's presents difficulties inobserving their internal status, and thus hinders the developments and applications of SoC's. This talk presents hardware techniques (IIP's, infrastructure intellectual properties) that can be integrated within a SoC to help the integration, analysis and debugging of embedded microprocessors and on-chip buses. This talk will also show how to use these techniques at various levels of the SoC development and applications, including ESL, RTL, FPGA and chip levels. A case study of using these techniques in a 3D graphics SoC will be presented.
Arithmetic Transform in Verification and Optimization of Datapath Circuits
Y. Pang
Friday, Nov. 27th, 9:30 a.m., Room MC603
Abstract
This talk will outline some recent exciting results on verifying and optimizing imprecise fixed point circuits, including the precision and range analysis and optimization.
Transaction Level-Based Design of Multi-core Embedded Systems
Prof. S. Abdi
Tuesday, Nov. 17th, 10:00 a.m., Room MC603
Abstract
The rising computation requirements of modern embedded applications, such as in multimedia, automotive and healthcare domains, have posed new challenges to the modeling and design of embedded systems. Embedded platforms may consist of multiple CPUs, DSPs and hardware accelerators, communicating over a network of buses. As a result of the design complexity, embedded system modeling is prohibitively expensive at the traditional cycle accurate level. Transaction level models (TLMs) are emerging as the next abstraction level, above the cycle accurate level, for fast and early system validation. However, new automation methods and tools are needed for using TLMs for design and implementation of multi-core embedded systems. In this talk, we will present some of our recent work on TLM-based design of multi-core embedded design. We will present our technique for automatic generation of fast cycle-approximate TLMs from a given mapping of the application to an embedded multicore platform. Our TLMs have been shown to execute two orders of magnitude faster than traditional instruction set simulation (ISS) and register-transfer level (RTL) models, while providing accurate timing estimation (less than 10 percent average error compared to board measurements). As a result, it is possible to reliably evaluate a design, optimize it, and regenerate a new TLM in a matter of minutes, as opposed to weeks or months of manual coding. The automatic TLM generation techniques have been implemented in a publicly available toolset called the Embedded System Environment (ESE).
Key Enabling Technologies for 3D IC Integration and SiP
Prof. John H. Lau
Thursday, Sept. 24th, 5:00 p.m., Room MC603
Abstract
Moore's law has been the most powerful driver for the development of the microelectronic industry. This law emphasizes on lithography scaling and integration (in 2D) of all functions on a single chip, perhaps through system-on-chip (SoC). On the other hand, the integration of all these functions can be achieved through system-in-package (SiP) or, ultimately, 3D IC integration, which is a very complicated subject. It involves component and system designs, FAB, packaging, testing, and materials and equipment suppliers. The key enabling technologies for 3D IC integration and wafer-level Packaging (WLP) are, e.g., electrical, optical, thermal, and mechanical designs and tests, known good die (KGD), TSV (through silicon vias) with RDL (redistribution layers), wafer thinning and thin wafer handling, thin chip strength measurement and improving, microbump forming and assembly, low temperature C2W and W2W bonding, embedded WLP, hybrid SiP, optical PCB, and thermal management. In this lecture, all these enabling technologies will be discussed. Most of the materials are based on the technical papers published within the past 3 years by the instructor and others.
Shimmer: Commercial WSN Networking Built on Ope n-source Software
Steve Ayer
Tue, May 12th, 9:00 a.m. , Room FDA6
Abstract
This talk presents the combination of software technologies built into Shimmer development kit that focus on the efficient design of WSN systems built on top of any WSN hardware. The abstraction techniques in operating systems, development languages and hardware configuration management allow rapid development of WSN applications. In the Shimmer kit, the techniques facilitated by TinyOS and NesC are demonstrated on a motion detector example. The Shimmer kit, built on IEEE 802.15.4 and Bluetooth wireless standards, employs ultra-low power MSP 430 nodes and a number of highly integrated components. Interference avoidance techniques are outlined, and the emerging, even more high-level development systems are briefly previewed.
OpenCL and Programming in a Multi-core Environment
Nathaniel Azuelos
Fri, Feb. 27th, 10:00 a.m., Room MC603
Abstract
As die sizes increase and chips become ever larger, including several CPU cores on a single die becomes a popular way of increasing computing power. A great deal of work has yielded several types of multi-core architectures in both the industry and academia. Unfortunately, the difficulties of multiprocessor programming, well studied as they are for some time, were inherited with the nominal increase in computing power, with a different set of challenges. Various architectures allow different degrees of abstraction from low-level primitives, ranging from full access (Cell Processor) to a certain level of opaqueness (Tesla architecture). In order to simplify application and scientific programmers access to libraries tailored to these architectures, an industry consortium (interestingly, Microsoft is not included) patched a common language/API standard named OpenCL. The language is made to simplify user access to multi-core programming, and includes features common to the new wave of powerful processors such as SIMD. In this presentation, we will attempt to present OpenCL in the context of the new computing world that is rapidly emerging.
Developing Scalable High Performance Systems at IBM
Nikola Grcevski
Tue, Oct. 14th, 9:15 a.m., Room TR1080
Abstract
Parallelization of software is increasingly becoming very important on modern computer architectures. Processor design trends are scaling outward by providing more cores rather than increasing the performance of individual ones. Almost all modern architectures are moving towards non-uniform memory access. We will discuss some of the issues around building scalable high performance multi-threaded systems, including leveraging built-in hardware support for parallel execution in microprocessors. This talk will also detail some ongoing development projects at the IBM Toronto Lab relating to scalability and execution parallelism.
A Proof of Correctness for the Construction of Property Monitors
Katell Morin-Allory
Mon, Jun. 2nd, 1:00 p.m., Room MC603
Abstract
We prove the correctness of an original method for generating components that capture the occurrence of events, and monitor logical and temporal properties of hardware/software embedded systems. The properties are written in PSL, under the form of assertions in declarative form. The method is based on a library of primitive digital components for the PSL temporal operators. These building blocks are interconnected to construct complex properties, resulting in a synthesizable digital module that can be properly linked to the digital system under scrutiny. In this presentation, I will focus on the proof of correctness.
System Verilog Assertion Enhancements for IEEE 1800 - 2008
Ed Cerny
Mon, Feb. 25th, 10:00 a.m., Room TR2120
Abstract
The SystemVerilog Language Reference Manual (LRM) is undergoing a major revision. There are important corrections, clarifications and many enhancements to the language. In this presentation we shall go over the main enhancements that have been proposed to the Systemverilog assertions. Most of them are close to being approved for inclusion in the 2008 LRM that is to become available in the 2nd half of 2008. The enhancements to assertions improve expressiveness, among others, by adding linear temporal operators, provide better usage of local variables, and define a special encapsulation for library checkers. Given the amount of information, the presentation will mainly make the audience aware of the new features but will not go into all the details. The interested persons may access the eda-stds.org Mantis web page to examine the various formal proposals as guests.
A Non-Linear Neural Classifier and its Applications in Testing Analog/RF Circuits
Yiorgos Makris
Fri, Feb. 22nd, 12:30 p.m., Room TR0060
Abstract
In this talk, we will be discussing a machine learning-based test paradigm for mixed-signal/RF circuits. We will first describe an ontogenic neural classifier that learns to separate the nominal from the faulty chip distributions in a low-dimensional space of inexpensive measurements. The key novelty of this classifier is that its topology is not fixed; rather, it adapts dynamically, in order to match the inherent complexity of the separation problem. Thus, it establishes separation hypersurfaces that reciprocate very well even in the presence of complex chip distributions. We will then discuss the construction of guard-bands, which provide a level-of-confidence indication and support a two-tier test method that allows exploration of the trade-off between test quality and test cost. In this method, the majority of chips are accurately classified through inexpensive measurements, while the small fraction of chips for which the decision of the classifier has a low level of confidence is re-tested through traditional specification testing. The ability of the proposed method to drastically reduce the cost of mixed-signal/RF testing without compromising its quality will be demonstrated using two example circuits, a switched-capacitor filter and a UHF receiver front-end. Additionally, its application in specification test compaction and its potential for developing a stand-alone analog/RF BIST method will be discussed.
HORUS: Provably-correct Construction for on-line Verification of Logical and Temporal Properties
Dominique Borrione
Thu, Jan. 10th, 11:00 a.m., Room McConnell 603
Abstract
The Horus tool developed at TIMA Laboratory supports the assertion-based verification and debugging method. Horus automatically generates Verilog or VHDL designs for: a) synchronous observation monitors b) test sequence generators c) history and interface mechanisms. The approach uses a (VHDL or Verilog) library of provably correct elementary components for the primitive operators of the standard PSL language. The interconnection method for these primitive components, also proven correct, is applied to obtain an efficient synthesizable VHDL or Verilog model. Once interconnected to the design under test, monitors and generators are used to observe its dynamic behavior, using simulation or emulation on a FPGA prototype. They can also be integrated on the same circuit, for online testing of safety critical applications.
The life of SPICE
Laurence W. Nagel
Thu, July 5th, 11:00 a.m., Trottier Room 2100
Abstract
The integrated circuit industry thrives on constant change and is not particularly known for tradition. It is curious, then, that the SPICE circuit simulation program, in one form or another, has been around the industry for over thirty years. That means that many engineers entering this booming business today weren?t even born when I released the first version of SPICE! In this talk, I will chart the journey of SPICE, starting as a teaching program at the University of California, Berkeley, and spreading into industry, launching a cottage industry of software houses writing and supporting "alphabet SPICE." I also will give credit to all of the early principals in this journey, and share some of my more amusing experiences during the journey. Nobody can say for sure, but I will offer my opinions on how this particular program has evolved in thirty years and yet stayed pretty much the same. I can think of no other computer program that can make that claim.
How CMC Can Help your Microsystems Research Objectives?
National Microelectronics and Photonics Testing Collaboratory
Wed, Jun 13, 1:30 p.m. Room 603
Does your research project include requirements for testing and validating high-performance microelectronic and photonic concepts? Learn how the wealth of test and measurement resources available through the National Microelectronics and Photonics Testing Collaboratory can help you achieve your research objectives. Join CMC Microsystems for an Information Session that will be organized at McGill.
The National Microelectronics and Photonics Testing Collaboratory is a Canada-wide initiative that brings world-class test capability, tools and technologies online for graduate students, faculty members and researchers at Canadian Universities.
Managed by CMC Microsystems, the ‘virtual laboratory’ facilitates both onsite and remote access to state-of-the-art, industry-grade equipment located at four specialized labs. These labs specialize in the verification and test of digital microelectronic technology, mixed-signal systems,
RF components and photonic systems.
You will hear directly from CMC’s test engineers about:
* The Testing Collaboratory and the capability available to you
* How you can access this capability
* How other university researchers have benefited from the Collaboratory
* The opportunity to participate in a remote test of your device or system
To register for evend and obtain more information please visit www.cmc.ca/test or contact Robert Mallard, Engineering Manager, Hybrid Packaging and Microsystems Test at rob_mallard@cmc.ca
Stephan Bourduas
A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing
Thu, May 3, 2:30 p.m. Room 544
A popular network topology for Network-on-Chip (NoC) implementations is the
two-dimensional mesh. A disadvantage of the mesh topology is in its large
communication radius. By partitioning a two-dimensional mesh into several
sub-meshes and connecting them using a global interconnect, we can reduce the
average number of hops for global traffic. This paper presents a hybrid
architecture that partitions a large 2D-mesh into several smaller sub-meshes
which are globally connected using a hierarchical ring interconnect.
Hierarchical rings have been selected for study because of their simplicity,
speed and efficiency in embedding onto a circuit layout, as well as for their
suitability for efficient cache coherent protocols. An original SystemC
modeling platform was implemented in order to compare the traditional 2D-mesh
with the hybrid ring/mesh architectures and the simulation results will show
that our hybrid architecture does indeed have a positive effect on the average
hop count.
Prof. Jonathan D. Farley
Distributive Lattices of Small Width: A problem from Stanley's Enumerative Combinatorics
Tuesday, April 3rd at 4pm
Location: McConnell 103
In Richard P. Stanley's 1986 text, Enumerative Combinatorics, the following problem is posed: Fix a natural number k. Consider the posets P of cardinality n such that, for 0 < i < n , P has exactly k order ideals (down-sets) of cardinality i . Let f_k(n) be the number of such posets. What is the generating function \sum f_k(n) x^n? I will give a solution to this problem (joint work with Ryan Klippenstine.) I will also relate this to a problem of Ivo Rosenberg (University of Montreal) from the 1981 Banff Conference on Ordered Sets.
Note: Prof. Farley (http://cisac.stanford.edu/people/lattice) is a winner of highest mathematical awards from Oxford University and Harvard University.
Feb. 28th, 9:30 a.m.
Room: 603
Dr. Yi Cai,
Agere, Allentown, PA
What will and EE do in an IC Company?
Design, Design for Testability and Testing Perspectives
Abstract: In this talk, we will discuss what the IC companies do for new product
development. We will describe the role of different job functions and their
interactions, and list out some current challenges that drive the
design, DFT and test innovations.