SoCs are currently using bus based interconnects like AMBA. It is also well understood that buses don't scale very well. NoC interconnects allow for more components to be connected together on a chip while still allowing high communication throughput.
My main focus has been on exploring alternative interconnect topologies for multi-processor NoCs. More specifically, I have been modeling a hierarchical ring interconnect in SystemC. I have implemented a custom platform in SystemC which enables me to quickly model different topologies as well as explore the effect of varying design parameters on the system performance.
Modeling in SystemC has limited usefulness; in order to more fully explore the feasibility of the hierarchical ring interconnect, the hierarchical ring interconnect was implemented in RTL (VHDL specifically) by a fellow Ph.D. student Jean-Samuel Chenard and myself. We also implemented a module which enables us to interface the interconnect with the AMBA bus implementation use in the Leon3 processor so that we can eventually synthesize a working NoC for FPGA implementation.
My general research interests are listed below: