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Publications

Conferences

  • Stephan Bourduas, Henry Chan and Zeljko Zilic, "Blocking-Aware Task Assignment for Wormhole Routed Network-on-Chip", Proceedings of 50th IEEE Int'l Midwest Symposium on Circuits & Systems/5th IEEE Int'l Northeast Workshop on Circuits & Systems, MWSCAS/NEWCAS 2007, August 2007
  • Stephan Bourduas and Zeljko Zilic, "Latency Reduction of Global Traffic in Wormwhole-routed Meshes Using Hierarchical Rings for Global Routing", Proceedings of 18th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2007, July 2007.
  • Stephan Bourduas and Zeljko Zilic, "A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing, Proceedings of International Symposium on Networks-on-Chips, NOCS 2007, Princeton, May 2007.
  • Stephan Bourduas, Jean-Samuel Chenard and Zeljko Zilic, “A RTL-Level Analysis of a Hierarchical Ring Interconnect for Network-on-Chip Multi-Processors”, Proceedings of International System-on-a-Chip Design Conference, ISOCC 2006 , Oct. 2006.
  • Stephan Bourduas, Benjamin Kuo, Zeljko Zilic and Naraig Manjikian, “Modeling and Evaluation of an Energy-Efficient Hierarchical Ring Interconnect for System-on-Chip Multiprocessors”, Proceedings of IEEE-NEWCAS Conference, Jun. 2006.
  • Stephan Bourduas, Ferhat Khendek, Daniel Vincent, "From MSC and UML to SDL”, 26th International Computer Software and Applications Conference (COMPSAC 2002), Prolonging Software Life: Development and Redevelopment, 26-29 August 2002, Oxford, England, Proceedings, IEEE Computer Society, ISBN: 0-7695-1727-7.
  • Ferhat Khendek, Stephan Bourduas, Daniel Vincent, “Stepwise Design With Message Sequence Charts”, Formal Techniques for Networked and Distributed Systems,FORTE 2001, Korea, Kluwer Academic Press, IFIP Conference Proceedings, ISBN: 0-7923-7470-3.

    • Workshop Papers

    • J-S. Chenard, S. Bourduas, M. Boule, and Z. Zilic, "Hardware Assertion Checkers in On-line Detection of Network-on-Chip Faults", Workshop on Diagnostic Services in Networks-on-Chips - Test, Debug and On-line Monitoring, Nice, April. 2007.
    • J-F. Boland, S. Bourduas, Y. Fan, Y. Wang and Z. Zilic, "Intellectual Core Design and Verification", TEXPO Exposition, CMC Symposium on Microelectronics Research and Development, Ottawa, Jun. 2002.

    Master's Thesis