Multiprocessor Network-on-Chip (NoC) SystemC simulation environment
A library of SystemC components have been implemented which enable prototyping different NoC interconnect topologies:
- Hierarchical rings: 4 local rings, 4 processing elements per ring.
- Wormhole routed mesh: Packets are are "worms" that reserve and release resources as they pass through the network.
- Hybrid Ring/Mesh: Hierarchical rings used for routing global trafﬁc and 2D-Mesh for local trafﬁc.
- In addition, I've implemented virtual channel wormhole routed versions of each architecture.
The SystemC platform has enabled me perform simulations and to collect data for several of my papers listed in my publications
Heterogeneous RTL implementation of a NoC
The NoC interconnect described above is currently being implemented in VHDL and will be used to connect several Leon3 processors as well as custom hardware modules together. The goal of the project is to eventually implement a working NoC on an FPGA.